//------------------------------------------------
// mipstest.v
//
// James Forrest, 2013
// Based on code by:
// David_Harris@hmc.edu 23 October 2005
//
// Testbench for MIPS processor
//------------------------------------------------

module topmips_tb();

    reg        clk, reset;
    wire       dp;
    wire [6:0] seg;
    wire [3:0] an;
    reg  [3:0] btn;
    reg  [7:0] sw;
    wire [7:0] led;

    // instantiate device to be tested
    //TopMips dut(clk, reset, 16'b0, memAddr, memData, memByteEn, memReadWriteBit, memEn, 1'b1);

    // generate interrupt signal
    initial begin
        btn = 4'd0; #222; btn = 4'd2;
    end

    TopMips dut(clk, reset, seg, dp, an, btn, sw, led);

    // initialize test
    initial begin
        reset <= 1; # 22; reset <= 0;
    end

    // generate clock to sequence tests
    always begin
        clk <= 1; #5;
        clk <= 0; #5;
    end

endmodule
